The present invention generally relates to advanced NAND memory technology. More specifically, the invention provides a repeatedly electrically erasable and programmable 2D or 3D NAND memory array comprising a unified multi-level hierarchical broken Bit Line (BL) structure that enables superfast and low-power Multiple Word Line (WL) and All-BL Simultaneous Erase, Erase-Verify, Program, Program-Verify and Read operations.
Conventionally, a 2D NAND flash includes several 2-dimensional (2D) planes on a common Triple P-well within a deep N-well on top of a common silicon P-substrate. When 2D NAND flash technology is scaled down below 2×nm for increasing NAND memory size, it hits the wall to meet the Moore's scaling law, good data reliability and short latency. The reliability issues include short data retention life cycle, high power-consumption and low Program, Erase and Read cycles. The slow latency issues include slow page-Read, page-Program, page-Program-verification, block-Erase and page-Erase-verification, etc.
The WL page size can be defined either in a large physical page size such as whole WL or a smaller logic size such as ½ or ¼ of a whole physical WL. The NAND's data storage types can be SLC, MLC, TLC, XLC or even an analog one that stores more than 16 states per one physical NAND cell, regardless of 2D or 3D NAND memory.
Recently, many new 3D NAND flash memory cells and array architectures have been proposed by using 3D transistors and Strings with a cylindrical column type structures such as a multiple-layer stacked vertical-channel (VCh1) 3D NAND technology from Toshiba, SanDisk and Samsung, or a vertical-gate (Vgat) NAND String technology from Samsung, and Macronix (Taiwan) and other 3D NAND flash technologies from Hynix, and Micron.
Although a 3D NAND flash memory has many advantages to use the less advanced technology nodes to increase NAND density over 1 Tb with a smaller silicon area than 2D NAND, it encounters new process disadvantages such as high aspect ratio, stair-case etching etc, more WL disturbance and new challenges to use the new scheme of gate-induced-drain-leakage (GIDL) current to erase the 3D NAND flash cells, etc.
Irrespective of 2D or 3D NAND flash pros and cons under development, there are many common long-held old and new problems not being completely solved and instead being mitigated when further scaling below 2×nm. For example, the conventional 20-year good SBPI (Self-Boosting-Program-Inhibit) scheme has been found un-reliable in Program and Program-Inhibit operations due to larger proximity coupling effects such as the charging and discharging of adjacent BL-BL coupling noises.
In other words, the conventional SBPI operations are strongly affected by the stored Vts of two surrounding NAND cells dispersed in the adjacent left and right BLs. These coupling noise effects greatly degrade the NAND data reliability and integrity, thus more errors and less P/E/R cycles are produced. As a result, more sophisticated ECC algorithms are required to use those NAND memories made of more advanced nodes below 3×nm.
As NAND density will be quickly exceeding 1 Tb with the circuit layout scaled down to 10 nm or below, more power consumptions and latencies in Read, Program, and Erase operations are commonly found in product specs. It is desirable to improve NAND memory technology to solve the above problems. The present invention provides a superfast, superior, and unified broken-BL hierarchical NAND array structure plus DRAM-like BL Charge-sharing and Sensing plus a novel Recall circuit aimed for implementing Multiple-WL and All-BL simultaneous Erase, Erase-Verify, Program, Program-Verify, and Read operations on today's 2D and 3D NAND flash designs without cell and process changes, as described throughout the specification and all figures.